The present invention relates generally to electronic systems and more particularly to systems and methods relating to memory validation.
Many electronic control systems are used in applications that require a high degree of dependability. Some of these applications are found in the automotive field where system failure could jeopardize passenger safety. While there are many implementations of such electronic systems, a certain group of implementations rely on redundancy to increase dependability. Such a redundant system might have multiple microprocessors, each having its own memory. While such systems provide increased dependability, they also have increased cost due to the extra components. As an alternative, other control systems reduce their cost by using a single memory array. Memory is typically a significant portion of the overall cost of a system. Other system components may or may not be duplicated. This second type of controller improves its dependability by performing validation routines to test at least some of its components, such as the memory. However, due to increased program size, increased feature sets, and increased memory size, the microprocessors in such systems are approaching bandwidth limitations with respect to executing real-time software validation routines. It would therefore be desirable if a system without redundant memory components could validate its memory for high dependability with reduced bandwidth requirements on the microprocessor.
Accordingly, there is a need for an improved electronic control system with memory validation and an accompanying method of operation.